A field effect transistor of which gate insulating material includes a ferroelectric (below, “ferroelectric gate field electric transistor” or “FeFET”) has in recent years been used for 64 kb NAND type flash memory array chips and has otherwise been marking important technical milestones. Compared with a conventional type of NAND flash memory, if applying FeFETs to a NAND flash memory (called “Fe-NAND”), the write voltage can be reduced to about one-third and therefore the endurance property of the number of times of program and erase cycling is remarkably good. That is, an Fe-NAND has the features of an energy saving, a memory which has high endurance property of the number of times of program and erase cycling. For use as a memory cell of a large scale integration memory, reduction of the dimensions of the FeFET has been demanded. To realize an FeFET with a small gate length Lg, the thickness of the gate insulator including the ferroelectric also usually has to be made thinner in terms of the fabrication process. If the thickness Li of the gate insulator with respect to Lg=1 μm is Li=400 nm, the aspect ratio of the cross-section of the gate insulator is a low A=Li/Lg=0.4 and there is little difficulty in the fabrication process such as the etching to form step differences and formation of a film covering step differences, but if becoming finer down to Lg=100 nm, Li=400 nm and A=4 result and the difficulty of the fabrication process increases. In a large scale integration memory, Lg becomes less than 100 nm and fine dimensions of down to 50 nm are sought. Inevitably, it will be demanded that Li be made smaller.
The fact that a transistor comprised of an insulating buffer layer Hf—Al—O formed on a silicon Si, further a ferroelectric layer formed on the insulating buffer layer Hf—Al—O, and further a gate metal formed on the ferroelectric layer is a ferroelectric gate field effect transistor excellent in data retention characteristic and pulse rewrite endurance property is disclosed in PLT 1. If an FeFET of which structure is Pt/SrBi2Ta2O9/Hf—Al—O/Si comprising a gate metal of Pt, a ferroelectric layer material of SrBi2Ta2O9, and an insulating buffer layer of Hf—Al—O formed on an Si substrate, as shown by the example in PLT 1, has a ferroelectric layer of a thickness of 400 nm, the memory window, by which the characteristic of the drain current Id with respect to the gate voltage Vg (Id-Vg characteristic) of the FeFET is shown, is 1.6V. In terms of an n-channel FeFET, the Id-Vg curve which is measured by increasing Vg from negative to positive and the Id-Vg curve which is measured by decreasing Vg from positive to negative exhibit different paths and have different threshold voltages. In other words, the Id-Vg curve which is measured by changing Vg from negative to positive and returning it to negative (or changing it from positive to negative and returning it to positive) draws a hysteresis curve. The difference in these threshold voltages is the “memory window”. In this Description, the voltages where Id=1×10−6 A on the two different paths are defined as the “threshold voltages” and the difference is defined as the “memory window”. Note that, in many cases, in the region smaller than the threshold voltages called the “subthreshold voltage”, no matter where the memory window is compared with, the memory window does not change much in size. The two states which correspond to the different threshold voltages are assigned the logical states of “0” and “1”. Which of these is “1” and which of these is “0” can be defined at each instance, and so it is not important. The 1.6V memory window can be said to be sufficient to discriminate the two states. When arranging a large number of FeFETs in an array to obtain a large scale integration memory, the variation in the two threshold voltages which correspond to the two states in the different FeFETs becomes a problem. The variation in threshold voltages of FeFETs is caused by variations in gate dimensions and film thickness etc. If the average value of the memory windows of a large number of FeFETs becomes so small as to be unable to be ignored compared with the variations in threshold values, sometimes error will occur in the discrimination of “0” and “1” of the FeFET forming a large scale integration memory. In general, the memory window of an FeFET forming a large scale integration memory is preferably large.